View DSP56F826E_2251008.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

56f800 16-bit digital signal controllers freescale.com 56f826 data sheet preliminary technical data dsp56f826 rev. 14 01/2007

56f826 technical data, rev. 14 freescale semiconductor 3 56f826 block diagram jtag/ once port program controller and hardware looping unit data alu 16 x 16 + 36 36-bit mac three 16-bit input registers two 36-bit accumulators address generation unit bit manipulation unit pll clock gen 16-bit 56800 core pab pdb xdb2 cgdb xab1 xab2 xtal extal interrupt controls ipbb controls ipbus bridge (ipbb) module controls address bus [8:0] data bus [15:0] cop reset applica- tion-specific memory & peripherals interrupt controller program memory 32252 x 16 flash 512 x 16 sram boot flash 2048 x 16 flash data memory 2048 x 16 flash 4096 x 16 sram cop/ watchdog sci0 & sci1 or spi0 ssi or gpio quad timer or gpio 4 6 4 16 16 v ddio v ssio v dda v ssa 6 44 spi1 or gpio 4 dedicated gpio 16 external bus interface unit external address bus switch bus control external data bus switch rd enable wr enable ds select[1] ps select[0] 16 16 d[00:15] a[00:15] or gpio clko reset irqa irqb extboot v dd v ss 3 4 tod timer low voltage superviso r analog reg 56f826 general description ? up to 40 mips at 80mhz core frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? hardware do and rep loops ? mcu-friendly instruction set supports both dsp and controller functions: mac, bit manipulation unit, 14 addressing modes ? 31.5k 16-bit words (64kb) program flash ? 512 16-bit words (1kb) program ram ?2k 16-bit words (4kb) data flash ?4k 16-bit words (8kb) data ram ?2k 16-bit words (4kb) bootflash ? up to 64k 16-bit words each of external memory expansion for program and data memory ? one serial port interface (spi) ? one additional spi or two optional serial communication in terfaces (sci) ? one synchronous serial interface (ssi) ? one general purpose quad timer ? jtag/once ? for debugging ? 100-pin lqfp package ? 16 dedicated and 30 shared gpio ? time-of-day (tod) timer
56f826 technical data, rev. 14 4 freescale semiconductor part 1 overview 1.1 56f826 features 1.1.1 processing core ? efficient 16-bit 56800 family controller engine with dual harvard architecture ? as many as 40 million instructions pe r second (mips) at 80mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? two 36-bit accumulators, including extension bits ? 16-bit bidirectional barrel shifter ? parallel instruction set with un ique processor addressing modes ? hardware do and rep loops ? three internal address buses and one external address bus ? four internal data buses and one external data bus ? instruction set supports both dsp and controller functions ? controller-style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stac k with depth limited only by memory ? jtag/once debug programming interface 1.1.2 memory ? harvard architecture permits as many as three simultaneous accesses to program and data memory ? on-chip memory including a low-cost, high-volume flash solution ?31.5k 16-bit words of program flash ?512 16-bit words of program ram ?2k 16-bit words of data flash ?4k 16-bit words of data ram ?2k 16-bit words of bootflash ? off-chip memory expansion ca pabilities programmable for 0, 4, 8, or 12 wait states ? as much as 64k 16-bit data memory ? as much as 64k 16-bit program memory 1.1.3 peripheral circuits for 56f826 ? one general purpose quad timer totalling 7 pins ? one serial peripheral interface with 4 pins (or four additional gpio lines) ? one serial peripheral interface, or multiplexe d with two serial comm unications interfaces totalling 4 pins ? synchronous serial interface ( ssi) with configurable six-pin po rt (or six additional gpio lines)
56f826 description 56f826 technical data, rev. 14 freescale semiconductor 5 ? sixteen (16) dedicated gene ral purpose i/o (gpio) pins ? thirty (30) shared general purpose i/o (gpio) pins ? computer-operating properly (cop) watchdog timer ? two external interrupt pins ? external reset pin for hardware reset ? jtag/on-chip emulation (once?) for unobtrusi ve, processor speed-ind ependent debugging ? software-programmable, phase locked loop-based frequency synthesizer for the controller core clock ? fabricated in high-density emos with 5v-tolerant, ttl-compatible digital inputs ? one time of day module 1.1.4 energy information ? dual power supply, 3.3v and 2.5v ? wait and multiple stop modes available 1.2 56f826 description the 56f826 is a member of the 56800 core-based family of processors. it combin es, on a single chip, the processing power of a dsp and the func tionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution for gene ral purpose applications. be cause of its low cost, configuration flexibility, and comp act program code, the 56f826 is we ll-suited for many applications. the 56f826 includes many peripherals that are especi ally useful for applications such as: noise suppression, id tag readers, sonic/ subsonic detectors, security acce ss devices, remote metering, sonic alarms, pos terminals, feature phones. the 56800 core is based on a harvard-style architectur e consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the microprocessor- style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both dsp and mcu applicati ons. the instruction set is also highly efficient for c/c++ compilers to enable rapid development of optimiz ed control applications. the 56f826 supports program executi on from either internal or extern al memories. two data operands can be accessed from the on-ch ip data ram per instruction cycle. the 56f826 also provides two external dedicated interrupt lines, and up to 46 general purpose input/output (gpi o) lines, depending on peripheral configuration. the 56f826 controller include s 31.5k words (16-bit) of program flash and 2k words of data flash (each programmable through the jtag port) wi th 512 words of program ram, and 4k words of data ram. it also supports program execu tion from external memory. the 56f826 incorporates a total of 2k words of b oot flash for easy customer-inclusion of field-programmable software routines that can be used to progr am the main program and data flash memory areas. both program and data flash memories can be independen tly bulk-erased or erased in page sizes of 256 words. the boot flash memory can also be either bulk- or page-erased.
56f826 technical data, rev. 14 6 freescale semiconductor this controller also provides a fu ll set of standard pr ogrammable periphe rals including one synchronous serial interface (ssi), one serial peripheral interface (spi), the option to select a second spi or two serial communications interfaces (scis), and one quad timer. the ssi, spi , and quad timer can be used as general purpose input/outputs (gpios) if a timer function is not required. 1.3 award-winning development environment ? processor expert tm (pe) provides a rapid application design (rad) tool that combines easy-to-use component-based software ap plication creation with an expert knowledge system. ? the code warrior integrated development environm ent is a sophisticated to ol for code navigation, compiling, and debugging. a complete set of eval uation modules (evms) and development system cards will support concurrent engineering. together, pe, code warrior and evms create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 product documentation the four documents listed in table 1-1 are required for a complete desc ription and proper design with the 56f826. documentation is available from local freescale distributor s, freescale semiconductor sales offices, freescale literature dist ribution centers, or online at www.freescale.com . table 1-1 56f826 chip documentation topic description order number 56800e family manual detailed description of the 56800 family architecture, and 16-bit core processor and the instruction set 56800efm dsp56f826/f827 user?s manual detailed description of memory, peripherals, and interfaces of the 56f826 and 56f827 dsp56f826-827um 56f826 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) dsp56f826 56f826 product brief summary description and block diagram of the 56f826 core, memory, periphe rals and interfaces dsp56f826pb 56f826 errata details any chip issues that might be present DSP56F826E
data sheet conventions 56f826 technical data, rev. 14 freescale semiconductor 7 1.5 data sheet conventions this data sheet uses the following conventions: overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. ?asserted? a high true (active high) signal is high or a low true (active low) signal is low. ?deasserted? a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for v il , v ol , v ih , and v oh are defined by individual product specifications. pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol
56f826 technical data, rev. 14 8 freescale semiconductor part 2 signal/connection descriptions 2.1 introduction the input and output signals of the 56f826 are organized into functional groups, as shown in table 2-1 and as illustrated in figure 2-1 . table 2-1 describes the signal or signals present on a pin. table 2-1 functional group pin allocations functional group number of pins power (v dd , v ddio or v dda ) (3,4,1) ground (v ss , v ssio or v ssa ) (3,4,1) pll and clock 3 address bus 1 16 data bus 1 16 bus control 4 quad timer module ports 1 4 jtag/on-chip emulation (once) 6 dedicated general pu rpose input/output 16 synchronous serial interface (ssi) port 1 6 serial peripheral interface (spi) port 1 1. alternately, gpio pins 4 serial communications interface (sci) ports 4 interrupt and program control 5
introduction 56f826 technical data, rev. 14 freescale semiconductor 9 figure 2-1 56f826 signals iden tified by functional group 1 1. alternate pin functionality is shown in parentheses. 56f826 2.5v power 3.3v analog power 3.3v power ground analog ground ground pll and clock external address bus or gpio external data bus external bus control dedicated gpio spi1 port or gpio sci0, sci1 port or spi0 port v dd v dda v ddio v ss v ssa v ssio extal xtal (clockin) clko a0-a7 (gpioe) a8-a15 (gpioa) d0?d15 ps ds rd wr ta0 (gpiof0) ta1 (gpiof1) ta2 (gpiof2) ta3 (gpiof3) tck tms tdi tdo trst de quad timer a or gpio jtag/once ? port gpiob0?7 gpiod0?7 srd (gpioc0) srfs (gpioc1) srck (gpioc2) std (gpioc3) stfs (gpioc4) stck (gpioc5) sclk (gpiof4) mosi (gpiof5) miso (gpiof6) ss (gpiof7) txd0 (sclk0) rxd0 (mosi0) txd1 (miso0) rxd1 (ss0 ) irqa irqb reset extboot ssi port or gpio 3 1 4 4* 1 4 1 1 1 8 8 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 interrupt/ program control 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * includes tcs pin, which is reserved for factory use and is tied to vss
56f826 technical data, rev. 14 10 freescale semiconductor 2.2 signals and package information all inputs have a weak internal pul l-up circuit associated with them. these pull-up circuits are always enabled. exceptions: 1. when a pin is owned by gpio, then the pull-up may be disabled under software control. 2. tck has a weak pull-down circuit always active. table 2-1 56f826 signal and packag e information for the 100 pin lqfp signal name pin no. type description v dd 20 v dd power ?these pins provide power to the inte rnal structures of the chip, and are generally connected to a 2.5v supply. v dd 64 v dd v dd 94 v dd v dda 59 v dda analog power ?this pin is a dedicated power pin for the analog portion of the chip and should be connected to a low-noise 3.3v supply. v ddio 5v ddio power in/out ?these pins provide power to the i/o structures of the chip, and are generally connected to a 3.3v supply. v ddio 30 v ddio v ddio 57 v ddio v ddio 80 v ddio v ss 19 v ss gnd? these pins provide grounding for the in ternal structures of the chip. all should be attached to v ss. v ss 63 v ss v ss 95 v ss v ssa 60 v ssa analog ground ?this pin supplies an analog ground. v ssio 6v ssio gnd in/out ?these pins provide grounding for the i/o ring on the chip. all should be attached to v ss. v ssio 31 v ssio v ssio 58 v ssio v ssio 81 v ssio tcs 99 input/output (schmitt) tcs ?this pin is reserved for factory use. it must be tied to v ss for normal use. in block diagrams, this pin is considered an additional v ss. extal 61 input external crystal oscillator input ?this input should be connected to a 4mhz external crystal or cerami c resonator. for more info rmation, please refer to section 3.6 .
signals and package information 56f826 technical data, rev. 14 freescale semiconductor 11 xtal (clockin) 62 output input crystal oscillator output ?this output connects the internal crystal oscillator output to an external crys tal or ceramic reso nator. if an external clock source over 4mhz is used, xtal must be used as the input and extal connected to v ss . for more information, please refer to section 3.6.3 . external clock input ?this input should be asserted when using an external clock or cera mic resonator. clko 65 output clock output ?this pin outputs a buffered clo ck signal. by programming the clko select register (clkosr), the us er can select between outputting a version of the signal applied to xtal and a version of the device master clock at the output of the pll. the clock fr equency on this pin can be disabled by programming the clko select register (clkosr). a0 (gpioe0) 24 output input/output address bus ?a0?a7 specify the address for external program or data memory accesses. port e gpio ?these eight general purpose i/o (gpio) pins can be individually programmed as input or output pins. after reset, the default state is address bus. a1 (gpioe1) 23 a2 (gpioe2) 22 a3 (gpioe3) 21 a4 (gpioe4) 18 a5 (gpioe5) 17 a6 (gpioe6) 16 a7 (gpioe7) 15 table 2-1 56f826 signal and package inform ation for the 100 pin lqfp (continued) signal name pin no. type description
56f826 technical data, rev. 14 12 freescale semiconductor a8 (gpioa0) 14 output input/output address bus ?a8?a15 specify the address for external program or data memory accesses. port a gpio ?these eight general purpose i/o (gpio) pins can be individually programmed as input or output pins. after reset, the default state is address bus. a9 (gpioa1) 13 a10 (gpioa2) 12 a11 (gpioa3) 11 a12 (gpioa4) 10 a13 (gpioa5) 9 a14 (gpioa6) 8 a15 (gpioa7) 7 d0 34 input/output data bus ? d0?d15 specify the data for external program or data memory accesses. d0?d15 are tri-stated when the external bus is inactive. d1 35 d2 36 d3 37 d4 38 d5 39 d6 40 d7 41 d8 42 d9 43 d10 44 d11 46 d12 47 d13 48 d14 49 d15 50 ps 29 output program memory select ?ps is asserted low for external program memory access. ds 28 output data memory select ?ds is asserted low for external data memory access. table 2-1 56f826 signal and package inform ation for the 100 pin lqfp (continued) signal name pin no. type description
signals and package information 56f826 technical data, rev. 14 freescale semiconductor 13 rd 26 output read enable ?rd is asserted during external memory read cycles. when rd is asserted low, pins d0?d15 become inputs and an external device is enabled onto the device data bus. when rd is deasserted high, the external data is latched inside the device. when rd is asserted, it qualifies the a0?a15, ps , and ds pins. rd can be connected directly to the oe pin of a static ram or rom. wr 27 output write enable ?wr is asserted during external memory write cycles. when wr is asserted low, pins d0?d15 become ou tputs and the device puts data on the bus. when wr is deasserted high, the external data is latched inside the external device. when wr is asserted, it qualifies the a0?a15, ps , and ds pins. wr can be connected directly to the we pin of a static ram. ta0 (gpiof0) 91 input/output input/output ta0?3 ?timer a channels 0, 1, 2, and 3 port f gpio ?these four general purpose i/o (gpio) pins can be individually programmed as input or output. after reset, the default state is quad timer. ta1 (gpiof1) 90 ta2 (gpiof2) 89 ta3 (gpiof3) 88 tck 100 input (schmitt) test clock input ?this input pin provides a gated clock to synchronize the test logic and shift serial data to the jtag/once port. the pin is connected internally to a pull-down resistor. tms 1 input (schmitt) test mode select input ?this input pin is used to sequence the jtag tap controller?s state machine. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. note: always tie the tms pin to v dd through a 2.2k resistor. tdi 2 input (schmitt) test data input ?this input pin provides a serial input data stream to the jtag/once port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. tdo 3 output test data output ?this tri-statable output pin pr ovides a serial output data stream from the jtag/once port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. trst 4 input (schmitt) test reset ?as an input, a low signal on this pin provides a reset signal to the jtag tap controller. to ensure complete hardware reset, trst should be asserted whenever reset is asserted. the only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset t he jtag/once module. in this case, assert reset , but do not assert trst . trst must always be asserted at power-up. note: for normal operation, connect trst directly to v ss . if the design is to be used in a debugging environment, trst may be tied to v ss through a 1k resistor. de 98 output debug event ?de provides a low pulse on recognized debug events. table 2-1 56f826 signal and package inform ation for the 100 pin lqfp (continued) signal name pin no. type description
56f826 technical data, rev. 14 14 freescale semiconductor gpiob0 66 input or output port b gpio ?these eight dedicated general purpose i/o (gpio) pins can be individually programmed as input or output pins. after reset, the default state is gpio input. gpiob1 67 gpiob2 68 gpiob3 69 gpiob4 70 gpiob5 71 gpiob6 72 gpiob7 73 gpiod0 74 input or output port d gpio ?these eight dedicated gpio pins can be individually programmed as an input or output pins. after reset, the default state is gpio input. gpiod1 75 gpiod2 76 gpiod3 77 gpiod4 78 gpiod5 79 gpiod6 82 gpiod7 83 srd (gpioc0) 51 input/output input/output ssi receive data (srd)? this input pin receives serial data and transfers the data to the ssi receive shift receiver. port c gpio ?this is a general purpose i/o (gpi o) pin with the capability of being individually programme d as input or output. after reset, the default state is gpio input. srfs (gpioc1) 52 input/ output input/output ssi serial receive frame sync (srfs)? this bidirectional pin is used by the receive section of the ssi as frame sync i/o or flag i/o. the stfs can be used only by the receiver. it is used to synchronize data transfer and can be an input or an output. port c gpio ?this is a general purpose i/o (gpi o) pin with the capability of being individually programme d as input or output. after reset, the default state is gpio input. table 2-1 56f826 signal and package inform ation for the 100 pin lqfp (continued) signal name pin no. type description
signals and package information 56f826 technical data, rev. 14 freescale semiconductor 15 srck (gpioc2) 53 input/output input/output ssi serial receive clock (srck)? this bidirectional pin provides the serial bit rate clock for the receive section of the ssi. the clock signal can be continuous or gated and can be used by both the tr ansmitter and receiver in synchronous mode. port c gpio? this is a general purpose i/o (gpi o) pin with the capability of being individually programme d as input or output. after reset, the default state is gpio input. std (gpioc3) 54 output input/output ssi transmit data (std)? this output pin transmits serial data from the ssi transmitter shift register. port c gpio? this is a general purpose i/o (gpi o) pin with the capability of being individually programme d as input or output. after reset, the default state is gpio input. stfs (gpioc4) 55 input input/output ssi serial transmit frame sync (stfs)? this bidirectional pin is used by the transmit section of the ssi as frame sync i/o or flag i/o. the stfs can be used by both the transmitter and receiver in synchronous mode. it is used to synchronize data transfer and can be an input or output pin. port c gpio? this is a general purpose i/o (gpi o) pin with the capability of being individually programme d as input or output. after reset, the default state is gpio input. stck (gpioc5) 56 input/ output input/output ssi serial transmit clock (stck)? this bidirectional pin provides the serial bit rate clock for the transmit section of the ssi. the clock signal can be continuous or gated. it can be used by both the tr ansmitter and receiver in synchronous mode. port c gpio? this is a general purpose i/o (gpi o) pin with the capability of being individually programme d as input or output. after reset, the default state is gpio input. sclk (gpiof4) 84 input/output input/output spi serial clock ?in master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. port f gpio ?this general purpose i/o (gpio) pin can be individually programmed as input or output. after reset, the default state is sclk. mosi (gpiof5) 85 input/output input/output spi master out/slave in (mosi) ?this serial data pin is an output from a master device and an input to a slave de vice. the master device places data on the mosi line a half-cycle before the clo ck edge that the slave device uses to latch the data. port f gpio ?this general purpose i/o (gpio) pin can be individually programmed as input or output. table 2-1 56f826 signal and package inform ation for the 100 pin lqfp (continued) signal name pin no. type description
56f826 technical data, rev. 14 16 freescale semiconductor miso (gpiof6) 86 input/output input/output spi master in/slave out (miso) ?this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high-impedance state if the slave device is not selected. port f gpio ?this general purpose i/o (gpio) pin can be individually programmed as input or output. after reset, the default state is miso. ss (gpiof7) 87 input input/output spi slave select ?in master mode, this pin is used to arbitrate multiple masters. in slave mode, this pin is used to select the slave. port f gpio ?this general purpose i/o (gpio) pin can be individually programmed as input or output. after reset, the default state is ss . txd0 (sclk0) 97 output input/output transmit data (txd0) ?transmit data output spi serial clock? in master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. after reset, the default state is sci output. rxd0 (mosi0) 96 input input/output receive data (rxd0) ? receive data input spi master out/slave in ?this serial data pin is an output from a master device, and an input to a slave device. the master device places data on the mosi line one half-cycl e before the clock edge the slave device uses to latch the data. after reset, the default state is sci input. txd1 (miso0) 93 output input/output transmit data (txd1) ?transmit data output spi master in/slave out? this serial data pin is an input to a master device and an output from a slave device. the miso lin e of a slave device is placed in the high-impedance state if the slave device is not selected. after reset, the default state is sci output. rxd1 (ss0 ) 92 input (schmitt) input receive data (rxd1) ? receive data input spi slave select ?in master mode, this pin is used to arbitrate multiple masters. in slave mode, this pin is used to select the slave. after reset, the default state is sci input. table 2-1 56f826 signal and package inform ation for the 100 pin lqfp (continued) signal name pin no. type description
signals and package information 56f826 technical data, rev. 14 freescale semiconductor 17 irqa 32 input (schmitt) external interrupt request a ?the irqa input is a synchronized external interrupt request that indica tes that an external device is requesting service. it can be programmed to be level-sensit ive or negative-e dge-triggered. if level-sensitive triggering is selected, an external pull-up resistor is required for wired-or operation. if the processor is in the stop state and irqa is asserted, the processor will exit the stop state. irqb 33 input (schmitt) external interr upt request b ?the irqb input is an external interrupt request that indicates that an external device is requesting service. it can be programmed to be level-sensitive or negat ive-edge-triggered. if level-sensitive triggering is selected, an external pu ll-up resistor is required for wired-or operation. reset 45 input (schmitt) reset ?this input is a direct hardware re set on the processor. when reset is asserted low, the device is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the external boot pin. the internal reset signal will be de asserted synchronous with the in ternal clocks, after a fixed number of internal clocks. to ensure complete hardware reset, reset and trst should be asserted together. the only exception occurs in a debugging environment when a hardware device reset is required a nd it is necessary not to reset the once/jtag module. in th is case, assert reset , but do not assert trst . extboot 25 input (schmitt) external boot ?this input is tied to v dd to force device to boot from off-chip memory. otherwise, it is tied to ground. table 2-1 56f826 signal and package inform ation for the 100 pin lqfp (continued) signal name pin no. type description
56f826 technical data, rev. 14 18 freescale semiconductor part 3 specifications 3.1 general characteristics the 56f826 is fabricated in high-de nsity cmos with 5v-tolerant ttl-c ompatible digital inputs. the term ? 5v-tolerant? refers to the capa bility of an i/o pin, built on a 3.3v-compatible process technology, to withstand a voltage up to 5.5v without damaging the device. many systems have a mixture of devices designed for 3.3v and 5v pow er supplies. in such systems, a bus may carry both 3.3v- and 5v-compatible i/o voltage levels. a standard 3.3v i/o is designed to recei ve a maximum voltage of 3.3v 10% during normal operation without causing damage . this 5v-tolerant capability, ther efore, offers the power savings of 3.3v i/o levels while being able to receive 5v levels wi thout being damaged. absolute maximum ratings given in table 3-1 are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliability or cause permanent damage to the device. the 56f826 dc/ac electrical specifi cations are preliminary and are from design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle. finalized specifications will be published af ter complete characterization a nd device qualificat ions have been completed. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
general characteristics 56f826 technical data, rev. 14 freescale semiconductor 19 table 3-1 absolute maximum ratings characteristic symbol min max unit supply voltage, core v dd 1 v ss ? 0.3 v ss + 3.0 v supply voltage, io supply voltage, analog v ddio 2 v dda 2 v ssio ? 0.3 v ssa ? 0.3 v ssio + 4.0 v ssa + 4.0 v digital input voltages analog input voltages - xtal, extal v in v ina v ssio ? 0.3 v ssa ? 0.3 v ssio + 5.5 v dda + 0.3 v voltage difference v dd to v dd_io , v dda v dd - 0.3 0.3 v voltage difference v ss to v ss _io , v ssa v ss - 0.3 0.3 v current drain per pin excluding v dd , v ss, v dda , v ssa, v ddio , v ssio i? 10 ma junction temperature t j ?150c storage temperature range t stg ? 55 150 c 1. v dd must not exceed v ddio 2. v ddio and v dda must not differ by more that 0.5v table 3-2 recommended operating conditions characteristic symbol min typ max unit supply voltage, core v dd 2.25 2.5 2.75 v supply voltage, io and analog v ddio, v dda 3.0 3.3 3.6 v voltage difference v dd to v dd_io , v dda v dd -0.1 - 0.1 v voltage difference v ss to v ss _io , v ssa v ss -0.1 - 0.1 v ambient operating temperature t a ?40 ? 85 c
56f826 technical data, rev. 14 20 freescale semiconductor notes: 1. theta-ja determined on 2s2p test boards is frequently lower than would be observed in an application. determined on 2s2p thermal test board. 2. junction to ambient therma l resistance, theta-ja ( r ja ) was simulated to be equivalent to the jedec specification jesd51-2 in a horizontal configuration in natural convection. theta-ja was also simulated on a thermal test board with two internal planes (2s2p, where ?s? is the numb er of signal layers and ?p? is the number of planes) per jesd51-6 and je sd51-7. the correct name for theta- ja for forced convection or with the non-single layer boards is theta-jma. 3. junction to case thermal resistance, theta-jc (r jc ), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the ?case? temperature. the basic cold plate measurement technique is described by mil-std 883d, method 1012.1. this is the correct thermal metric to use to calculate thermal performance wh en the package is being used with a heat sink. 4. thermal characterization parameter, psi-jt ( jt ), is the ?resistance? from junction to reference point thermocouple on top center of case as defined in jesd51-2. jt is a useful value to use to estimate junction temperature in steady stat e customer environments. 5. junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temper ature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. see section 5.1 for more details on thermal design considerations. 7. tj = junction temperature ta = ambient temperature table 3-3 thermal characteristics 6 characteristic comments symbol value unit notes 100-pin lqfp junction to ambient natural convection r ja 48.3 c/w 2 junction to ambient (@1m/sec) r jma 43.9 c/w 2 junction to ambient natural convection four layer board (2s2p) r jma (2s2p) 40.7 c/w 1.2 junction to ambient (@1m/sec) four layer board (2s2p) r jma 38.6 c/w 1,2 junction to case r jc 13.5 c/w 3 junction to center of case jt 1.0 c/w 4, 5 i/o pin power dissipation p i/o user determined w power dissipation p d p d = (i dd x v dd + p i/o )w junction to center of case p dmax (tj - ta) /r ja w7
dc electrical characteristics 56f826 technical data, rev. 14 freescale semiconductor 21 3.2 dc electrical characteristics table 3-4 dc electr ical characteristics operating conditions: v ssio =v ss = v ssa = 0v, v dda =v ddio =3.0?3.6v, v dd = 2.25?2.75v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz characteristic symbol min typ max unit input high voltage (xtal/extal) v ihc 2.25 ? 3.6 v input low voltage (xtal/extal) v ilc 0?0.5v input high voltage (schmitt trigger inputs) 1 v ihs 2.2 ? 5.5 v input low voltage (schmitt trigger inputs) 1 v ils -0.3 ? 0.8 v input high voltage (all other digital inputs) v ih 2.0 ? 5.5 v input low voltage (all other digital inputs) v il -0.3 ? 0.8 v input current high (pull-up/p ull-down resistors disabled, v in =v dd ) i ih -1 ? 1 a input current low (pull-up/pu ll-down resistors disabled, v in =v ss ) i il -1 ? 1 a input current high (with pull-up resistor, v in =v dd )i ihpu -1 ? 1 a input current low (wit h pull-up resistor, v in =v ss )i ilpu -210 ? -50 a input current high (with pull-down resistor, v in =v dd )i ihpd 20 ? 180 a input current low (with pull-down resistor, v in =v ss )i ilpd -1 ? 1 a nominal pull-up or pull-down resistor value r pu , r pd 30 k output tri-state current low i ozl -10 ? 10 a output tri-state current high i ozh -10 ? 10 a input current high (analog inputs, v in =v dda ) 2 i iha -15 ? 15 a input current low (analog inputs, v in =v ssa ) 2 i ila -15 ? 15 a output high voltage (at ioh) v oh v dd ? 0.7 ? ? v output low voltage (at iol) v ol ??0.4v output source current i oh 4??ma output sink current i ol 4??ma pwm pin output source current 3 i ohp 10 ? ? ma pwm pin output sink current 4 i olp 16 ? ? ma
56f826 technical data, rev. 14 22 freescale semiconductor input capacitance c in ?8?pf output capacitance c out ?12?pf v dd supply current i ddt 5 run 6 ?4775ma wait 7 ?2136ma stop ?28ma low voltage interrupt, v ddio power supply 8 v eio 2.4 2.7 3.0 v low voltage interrupt, v dd power supply 9 v eic 2.0 2.2 2.4 v power on reset 10 v por ?1.72.0v 1. 1. schmitt trigger inputs are: extboot, irqa , irqb , reset , tcs, tck, trst , tms, tdi and rxd1 2. analog inputs are: ana[0:7], xtal and extal. specification assumes adc is not sampling. 3. pwm pin output source current measured with 50% duty cycle. 4. pwm pin output sink current measured with 50% duty cycle. 5. i ddt = i dd + i dda (total supply current for v dd + v dda ) 6. run (operating) i dd measured using 4mhz cloc k source. all inputs 0.2v from rail; outputs unloaded. all ports configured as inputs; measured with all modules enabled. 7. wait i dd measured using external s quare wave clock source (f osc = 4mhz) into xtal; all inputs 0.2v from rail; no dc loads; less than 50pf on all outputs. c l = 20pf on extal; all ports configured as input s; extal capacitance linearly affects wait i dd ; measured with pll enabled. 8. this low-voltage interrupt monitors the v ddio power supply. if v ddio drops below v eio , an interrupt is generated. functionality of the device is guaranteed under transient conditions when v ddio > v eio (between the minimum specified v ddio and the point when the v eio interrupt is generated). 9. this low-voltage interrupt monitors thev dd power supply. if v ddio drops below v eic , an interrupt is generated. functionality of the device is guaranteed under tr ansient conditions when v dd > v eic (between the minimum specified v dd and the point when the v eic interrupt is generated). 10. power ? on reset occurs whenever the v dd power supply drops below v por . while power is ramping up, this signal remains active for as long as v dd is below v por no matter how long the ramp-up rate is. table 3-4 dc electrical characteristics (continued) operating conditions: v ssio =v ss = v ssa = 0v, v dda =v ddio =3.0?3.6v, v dd = 2.25?2.75v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz characteristic symbol min typ max unit
supply voltage sequencing and separation cautions 56f826 technical data, rev. 14 freescale semiconductor 23 figure 3-1 maximum run idd vs. frequency (see note 6. in table 3-4 ) 3.3 supply voltage sequencing and separation cautions figure 3-2 shows two situations to avoid in sequencing the v dd and v ddio, v dda supplies. notes: 1. v dd rising before v ddio , v dda 2. v ddio , v dda rising much faster than v dd figure 3-2 supply voltage seque ncing and separation cautions 0 25 75 100 50 20 40 60 80 freq. (mhz) idd (ma) idd digital idd analog idd total 3.3v 2.5v time 0 2 1 supplies stable v dd v ddio, v dda dc power supply voltage
56f826 technical data, rev. 14 24 freescale semiconductor v dd should not be allowed to rise ea rly (1). this is usua lly avoided by running the regulator for the v dd supply (2.5v) from the voltage generated by the 3.3v v ddio supply, see figure 3-3 . this keeps v dd from rising faster than v ddio . v dd should not rise so late that a large voltage difference is al lowed between the two supplies (2). typically this situation is avoided by using external di screte diodes in series between supplies, as shown in figure 3-3 . the series diodes forward bias when the difference between v ddio and v dd reaches approximately 1.4, causing v dd to rise as v ddio ramps up. when the v dd regulator begins proper operation, the difference between suppl ies will typically be 0.8v and conduction thr ough the diode chain reduces to essentially leakage current. during supply se quencing, the following general relationship should be adhered to: v ddio > v dd > (v ddio - 1.4v) in practice, v dda is typically connected directly to v ddio with some filtering. figure 3-3 example circuit to control supply sequencing 3.4 ac electrical characteristics timing waveforms in section 3.4 are tested using the v il and v ih levels specified in the dc characteristics table. the levels of v ih and v il for an input signal are shown in figure 3-4 . figure 3-4 input signal measurement references figure 3-5 shows the definitions of the following signal states: ? active state, when a bus or signal is driven, and enters a low impedance state ? tri-stated, when a bus or signal is placed in a high impedance state ? data valid state, when a signal level has reached v ol or v oh ? data invalid state, when a signal level is in transition between v ol and v oh 3.3v regulator 2.5v regulator supply v dd v ddio, v dda v ih v il fall time input signal note: the midpoint is v il + (v ih ? v il )/2. midpoint1 low high pulse width 90% 50% 10% rise time
flash memory characteristics 56f826 technical data, rev. 14 freescale semiconductor 25 figure 3-5 signal states 3.5 flash memory characteristics table 3-5 flash memory truth table mode xe 1 1. x address enable, all rows are disabled when xe = 0 ye 2 2. y address enable, ymux is disabled when ye = 0 se 3 3. sense amplifier enable oe 4 4. output enable, tri-state flash data out bus when oe = 0 prog 5 5. defines program cycle erase 6 6. defines erase cycle mas1 7 7. defines mass erase cyc le, erase whole block nvstr 8 8. defines non-volatile store cycle standby l l l l l l l l read hhhh l l l l word program h h l l h l l h page erase h l l l l h l h mass erase h l l l l h h h table 3-6 ifren truth table mode ifren = 1 ifren = 0 read read information block read main memory block word program program information block program main memory block page erase erase information block erase main memory block mass erase erase both block e rase main memory block data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active
56f826 technical data, rev. 14 26 freescale semiconductor table 3-7 flash timing parameters operating conditions: v ss = v ssa = 0 v, v dd = v dda = 3.0?3.6v, t a = ?40 to +85 c, c l 50pf characteristic symbol min typ max unit figure program time t prog* 20 ? ? us figure 3-6 erase time t erase* 20 ? ? ms figure 3-7 mass erase time t me* 100 ? ? ms figure 3-8 endurance 1 1. one cycle is equal to an erase program and read. e cyc 10,000 20,000 ? cycles data retention 1 d ret 10 30 ? years the following parameters should only be used in the manual word programming mode prog/erase to nvstr set up time t nvs* ?5?us figure 3-6 , figure 3-7 , figure 3-8 nvstr hold time t nvh* ?5?us figure 3-6 , figure 3-7 nvstr hold time (mass erase) t nvh1* ?100?us figure 3-8 nvstr to program set up time t pgs* ?10?us figure 3-6 recovery time t rcv* ?1?us figure 3-6 , figure 3-7 , figure 3-8 cumulative program hv period 2 2. thv is the cumulative high voltage programming time to the same row before next erase. the same address cannot be programmed twice before next erase. t hv ?3?ms figure 3-6 program hold time 3 3. parameters are guaranteed by design in smart pr ogramming mode and must be one cycle or greater. *the flash interface unit provides registers for the control of these parameters. t pgh ??? figure 3-6 address/data set up time 3 t ads ??? figure 3-6 address/data hold time 3 t adh ??? figure 3-6
flash memory characteristics 56f826 technical data, rev. 14 freescale semiconductor 27 figure 3-6 flash program cycle figure 3-7 flash erase cycle xadr yadr ye din prog nvstr tnvs tpgs tadh tprog tads tpgh tnvh trcv thv ifren xe xadr ye=se=oe=mas1=0 erase nvstr tnvs tnvh trcv terase ifren xe
56f826 technical data, rev. 14 28 freescale semiconductor figure 3-8 flash ma ss erase cycle 3.6 external clock operation the 56f826 system clock can be derived from a crystal or an external sy stem clock signal. to generate a reference frequency using the intern al oscillator, a reference crysta l must be connected between the extal and xtal pins. 3.6.1 crystal oscillator the internal oscillator is also designed to interfac e with a parallel-resonant crystal resonator in the frequency range specified fo r the external crystal in table 3-9 . a recommended crysta l oscillator circuit is shown in figure 3-9 . follow the crystal supplie r?s recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximu m stability and reliable start-up. the crystal and associated components shoul d be mounted as close as possible to the extal and xtal pins to minimize output distortion and start-up stabil ization time.the internal 56f82x oscillator circuitry is designed to have no external load capacitors present. as shown in figure 3-9 , no external load capacitors should be used. the 56f80x components internally are modeled as a pa rallel resonant oscillator circuit to provide a capacitive load on each of the osci llator pins (xtal and extal) of 10pf to 13pf over temperature and process variations. using a typical value of internal capacitance on these pins of 12pf and a value of 3pf xadr ye=se=oe=0 erase nvstr tnvs tnvh1 trcv tme mas1 ifren xe
external clock operation 56f826 technical data, rev. 14 freescale semiconductor 29 as a typical circuit board trace capaci tance the parallel load capacitance presented to the crystal is 9pf as determined by the following equation: this is the value load capacitance that should be us ed when selecting a crysta l and determining the actual frequency of operation of the crystal oscillator circuit. figure 3-9 connecting to a cr ystal oscillator circuit 3.6.2 ceramic resonator it is also possible to drive the in ternal oscillator with a ceramic re sonator, assuming the overall system design can tolerate the reduced signal integrity. a typical ceramic resona tor circuit is shown in figure 3-10 . refer to supplier?s recommendations when selecting a ceramic resonator and associated components. the resonator and com ponents should be mounted as clos e as possible to the extal and xtal pins. the internal 56f82x os cillator circuitry is designed to have no external load capacitors present. as shown in figure 3-10 , no external load capacitors should be used. figure 3-10 connecting a ceramic resonator note: freescale recommends only two terminal ceram ic resonators vs. three terminal resonators (which contain an internal bypass capacitor to ground). cl = cl1 * cl2 cl1 + cl2 + cs = + 3 = 6 + 3 = 9pf 12 * 12 12 + 12 recommended external crystal parameters: r z = 1 to 3m f c = 4mhz (optimized for 4mhz) extal xtal r z f c recommended ceramic resonator parameters: r z = 1 to 3 m f c = 4mhz (optimized for 4mhz) extal xtal r z f c
56f826 technical data, rev. 14 30 freescale semiconductor 3.6.3 external clock source the recommended method of connecting an external clock is given in figure 3-11 . the external clock source is connected to xtal and the extal pin is held v dda /2. figure 3-11 connecting an external clock signal figure 3-12 external clock timing table 3-8 external clock op eration timing requirements operating conditions: v ssio =v ss = v ssa = 0v, v dda =v ddio =3.0?3.6v, v dd = 2.25?2.75v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz characteristic symbol min typ max unit frequency of operation (external clock driver) 1 1. see figure 3-11 for details on using the recommended c onnection of an external clock driver. f osc 04 80 2 2. when using time of day (tod), ma ximum external frequency is 6mhz. mhz clock pulse width 3, 4 3. the high or low pulse width must be no smaller than 6.25ns or the chip will not function. 4. parameters listed are guaranteed by design. t pw 6.25 ? ? ns 56f826 xtal extal external v dda /2 clock external clock v ih v il note: the midpoint is v il + (v ih ? v il )/2. 90% 50% 10% 90% 50% 10% t pw t pw
external bus asynchronous timing 56f826 technical data, rev. 14 freescale semiconductor 31 3.6.4 phase locked loop timing 3.7 external bus asynchronous timing table 3-9 pll timing operating conditions: v ssio = v ss = v ssa = 0v, v dda = v ddio = 3.0?3.6v, v dd = 2.25?2.75v, t a = ?40 to +85 c, c l < 50pf, f op = 80mhz characteristic symbol min typ max unit external reference cryst al frequency for the pll 1 1. an externally supplied reference cl ock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 4mhz input crystal. f osc 246mhz pll output frequency 2 2. zclk may not exceed 80mhz. for additional information on zclk and f out /2, please refer to the occs chapter in the user manual. zclk = f op f out /2 40 ? 110 mhz pll stabilization time 3 -40 o to +85 o c 3. this is the minimum time required after the pll set-up is changed to ensure reliable operation. t plls ?110ms table 3-10 external bus asynchronous timing 1, 2 operating conditions: v ssio = v ss = v ssa = 0v, v dda = v ddio = 3.0?3.6v, v dd = 2.25?2.75v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz characteristic symbol min max unit address valid to wr asserted t awr 6.5 ? ns wr width asserted wait states = 0 wait states > 0 t wr 7.5 (t*ws) + 7.5 ? ? ns ns wr asserted to d0?d15 out valid t wrd ?t + 4.2ns data out hold time from wr deasserted t doh 4.8 ? ns data out set up time to wr deasserted wait states = 0 wait states > 0 t dos 2.2 (t*ws) + 6.4 ? ? ns ns rd deasserted to address not valid t rda 0?ns address valid to rd deasserted wait states = 0 wait states > 0 t ardd 18.7 (t*ws) + 18.7 ? ns ns
56f826 technical data, rev. 14 32 freescale semiconductor input data hold to rd deasserted t drd 0?ns rd assertion width wait states = 0 wait states > 0 t rd 19 (t*ws) + 19 ? ? ns ns address valid to input data valid wait states = 0 wait states > 0 t ad ? ? 1 (t*ws) + 1 ns ns address valid to rd asserted t arda -4.4 ? ns rd asserted to input data valid wait states = 0 wait states > 0 t rdd ? ? 2.4 (t*ws) + 2.4 ns ns wr deasserted to rd asserted t wrrd 6.8 ? ns rd deasserted to rd asserted t rdrd 0?ns wr deasserted to wr asserted t wrwr 14.1 ? ns rd deasserted to wr asserted t rdwr 12.8 ? ns 1. timing is both wait state- and frequency-dependent. in the fo rmulas listed, ws = the number of wait states and t = clock period. for 80mhz operation, t = 12.5ns. 2. parameters listed are guaranteed by design. to calculate the required access time for an external memory for any frequency < 80mhz, use this formula: top = clock period @ desired operating frequency ws = number of wait states memory access time = (top*ws) + (top- 11.5) table 3-10 external bus asynchronous timing 1, 2 (continued) operating conditions: v ssio = v ss = v ssa = 0v, v dda = v ddio = 3.0?3.6v, v dd = 2.25?2.75v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz characteristic symbol min max unit
external bus asynchronous timing 56f826 technical data, rev. 14 freescale semiconductor 33 figure 3-13 external bu s asynchronous timing a0?a15, ps , ds (see note) wr d0?d15 rd note: during read-modify-write instructions and internal instructions , the address lines do not change state. data in data out t awr t arda t ardd t rda t rd t rdrd t rdwr t wrwr t wr t dos t wrd t wrrd t ad t doh t drd t rdd
56f826 technical data, rev. 14 34 freescale semiconductor 3.8 reset, stop, wait, mode select, and interrupt timing table 3-11 reset, stop, wait, mode select, and interrupt timing 1, 5 operating conditions: v ssio = v ss = v ssa = 0v, v dda = v ddio = 3.0?3.6v, v dd = 2.25?2.75v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz 1. in the formulas, t = clock cycle. for an operating frequency of 80mhz, t = 12.5ns. characteristic symbol min max unit see figure reset assertion to address, data and control signals high impedance t raz ?21ns figure 3-14 minimum reset assertion duration 2 omr bit 6 = 0 omr bit 6 = 1 2. circuit stabilization del ay is required during reset when using an exter nal clock or crystal os cillator in two cases: ? after power-on reset ? when recovering from stop state t ra 275,000t 128t ? ? ns ns figure 3-14 reset deassertion to first ex ternal address output t rda 33t 34t ns figure 3-14 edge-sensitive interrupt request width t irw 1.5t ? ns figure 3-15 irqa , irqb assertion to exte rnal data memory access out valid, caused by first instruction execution in the interrupt service routine t idm 15t ? ns figure 3-16 irqa , irqb assertion to gener al purpose output valid, caused by first instruction execution in the interrupt service routine t ig 16t ? ns figure 3-16 irqa low to first valid inte rrupt vector address out recovery from wait state 3 3. the minimum is specified for the duration of an edge-sensitive irqa interrupt required to recover from the stop state. this i s not the minimum required so that the irqa interrupt is accepted. t iri 13t ? ns figure 3-17 irqa width assertion to recover from stop state 4 4. the interrupt instruction fetch is visible on the pins only in mode 3. 5. parameters listed are guaranteed by design. t iw 2t ? ns figure 3-18 delay from irqa assertion to fetch of first instruction (exiting stop) omr bit 6 = 0 omr bit 6 = 1 t if ? ? 275,000t 12t ns ns figure 3-18 duration for level sensitive irqa assertion to cause the fetch of first irqa interrupt instruction (exiting stop) omr bit 6 = 0 omr bit 6 = 1 t irq ? ? 275,000t 12t ns ns figure 3-19 delay from level sensitive irqa assertion to first interrupt vector address out valid (exiting stop) omr bit 6 = 0 omr bit 6 = 1 t ii ? ? 275,000t 12t ns ns figure 3-19
reset, stop, wait, mode select, and interrupt timing 56f826 technical data, rev. 14 freescale semiconductor 35 figure 3-14 asynchronous reset timing figure 3-15 external interrupt ti ming (negative-edge-sensitive) figure 3-16 external level-s ensitive interrupt timing first fetch a0?a15, d0?d15 ps , ds , rd , wr reset first fetch t ra t raz t rda irqa , irqb t irw a0?a15, ps , ds , rd , wr irqa , irqb first interrupt instruction execution a) first interrupt instruction execution general purpose i/o pin irqa , irqb b) general purpose i/o t idm t ig
56f826 technical data, rev. 14 36 freescale semiconductor figure 3-17 interrupt fr om wait state timing figure 3-18 recovery from stop state using asynchronous interrupt timing figure 3-19 recovery from stop state using irqa interrupt service instruction fetch irqa , irqb first interrupt vector a0?a15, ps , ds , rd , wr t iri not irqa interrupt vector irqa a0?a15, ps , ds , rd , wr first instruction fetch t iw t if instruction fetch irqa a0?a15 ps , ds , rd , wr first irqa interrupt t irq t ii
serial peripheral interface (spi) timing 56f826 technical data, rev. 14 freescale semiconductor 37 3.9 serial peripheral interface (spi) timing table 3-12 spi timing 1 operating conditions: v ssio =v ss = v ssa = 0v, v dda =v ddio =3.0?3.6v, v dd = 2.25?2.75v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz 1. parameters are guaranteed by design. characteristic symbol min max unit see figure cycle time master slave t c 50 25 ? ? ns ns figures 3-20 , 3-21 , 3-22 , 3-23 enable lead time master slave t eld ? 25 ? ? ns ns figure 3-23 enable lag time master slave t elg ? 100 ? ? ns ns figure 3-23 clock (sclk) high time master slave t ch 24 12 ? ? ns ns figures 3-20 , 3-21 , 3-22 , 3-23 clock (sclk) low time master slave t cl 24.1 12 ? ? ns ns figures 3-20 , 3-21 , 3-22 , 3-23 data set-up time required for inputs master slave t ds 20 0 ? ? ns ns figures 3-20 , 3-21 , 3-22 , 3-23 data hold time required for inputs master slave t dh 0 2 ? ? ns ns figures 3-20 , 3-21 , 3-22 , 3-23 access time (time to data active from high-impedance state) slave t a 4.8 15 ns figure 3-23 disable time (hold time to high-impedance state) slave t d 3.7 15.2 ns figure 3-23 data valid for outputs master slave (after enable edge) t dv ? ? 4.5 20.4 ns ns figures 3-20 , 3-21 , 3-22 , 3-23 data invalid master slave t di 0 0 ? ? ns ns figures 3-20 , 3-21 , 3-22 , 3-23 rise time master slave t r ? ? 11.5 10.0 ns ns figures 3-20 , 3-21 , 3-22 , 3-23 fall time master slave t f ? ? 9.7 9.0 ns ns figures 3-20 , 3-21 , 3-22 , 3-23
56f826 technical data, rev. 14 38 freescale semiconductor figure 3-20 spi master timing (cpha = 0) figure 3-21 spi master timing (cpha = 1) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in master msb out bits 14?1 master lsb out ss (input) ss is held high on master t r t f t f t di t ds t di (ref) t dv t ch t dh t c t r t f t r t cl t ch t cl sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in master msb out bits 14? 1 master lsb out ss (input) ss is held high on master t c t cl t f t di t dv (ref) t dv t r t dh t ds t r t ch t ch t cl t f t r t f
serial peripheral interface (spi) timing 56f826 technical data, rev. 14 freescale semiconductor 39 figure 3-22 spi slave timing (cpha = 0) figure 3-23 spi slave timing (cpha = 1) sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 msb in bits 14?1 lsb in ss (input) slave lsb out t elg t f t r t c t cl t ch t cl t eld t a t ch t r t f t d t di t di t ds t dh t dv sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 msb in bits 14?1 lsb in ss (input) slave lsb out t c t cl t dv t a t eld t r t f t elg t ch t cl t ch t f t ds t dv t di t dh t d t r
56f826 technical data, rev. 14 40 freescale semiconductor 3.10 synchronous serial interface (ssi) timing table 3-13 ssi master mode 1 switching characteristics operating conditions: v ssio = v ss = v ssa = 0v, v dda = v ddio = 3.0?3.6v, v dd = 2.25?2.75v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz 1. master mode is internally generated clocks and frame syncs parameter symbol min typ max units stck frequency fs 10 2 2. max clock frequency is ip_clk/4 = 40m hz / 4 = 10mhz for an 80mhz part. mhz stck period 3 t sckw 100 ? ? ns stck high time t sckh 50 4 ??ns stck low time t sckl 50 4 ??ns output clock rise/fall time (stck, srck) ? 4 ?ns delay from stck high to stfs (bl) high - master 5 t tfsbhm 0.1 ? 0.5 ns delay from stck high to stfs (wl) high - master 5 t tfswhm 0.1 ? 0.5 ns delay from srck high to srfs (bl) high - master 5 t rfsbhm 0.6 ? 1.3 ns delay from srck high to srfs (wl) high - master 5 t rfswhm 0.6 ? 1.3 ns delay from stck high to stfs (bl) low - master 5 t tfsblm -1.0 ? -0.1 ns delay from stck high to stfs (wl) low - master 5 t tfswlm -1.0 ? -0.1 ns delay from srck high to srfs (bl) low - master 5 t rfsblm -0.1 ? 0 ns delay from srck high to srfs (wl) low - master 5 t rfswlm -0.1 ? 0 ns stck high to stxd enable from high impedance - master t txem 20 ? 22 ns stck high to stxd valid - master t txvm 24 ? 26 ns stck high to stxd not valid - master t txnvm 0.1 ? 0.2 ns stck high to stxd high impedance - master t txhim 24 ? 25.5 ns srxd setup time before srck low - master t sm 4?? ns srxd hold time after srck low - master t hm 4?? ns synchronous operation (in addition to standard internal clock parameters) srxd setup time before stck low - master t tsm 4?? srxd hold time after stck low - master t thm 4??
synchronous serial interface (ssi) timing 56f826 technical data, rev. 14 freescale semiconductor 41 figure 3-24 master mo de timing diagram 3. all the timings for the ssi are given for a non-inverted se rial clock polarity (tsckp=0 in scr2 and rsckp=0 in scsr) and a non-inverted frame sync (tfsi=0 in scr2 and rfsi=0 in scsr ). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the cl ock signal stck/srck and/or the frame sync stfs/srfs in the tables and in the figures. 4. 50% duty cycle 5. bl = bit length; wl = word length t thm t tsm t hm t sm t rfswlm t rfswhm t rfblm t rfsbhm t txhim t txnvm t txvm t txem t tfswlm t tfswhm t tfsblm t tfsbhm t sckl t sckw t sckh first bit last bit stck output stfs (bl) output stfs (wl) output stxd srck output srfs (bl) output srfs (wl) output srxd
56f826 technical data, rev. 14 42 freescale semiconductor table 3-14 ssi slave mode 1 switching characteristics operating conditions: v ssio = v ss = v ssa = 0v, v dda = v ddio = 3.0?3.6v, v dd = 2.25?2.75v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz parameter symbol min typ max units stck frequency fs ? 10 2 mhz stck period 3 t sckw 100 ? ? ns stck high time t sckh 50 4 ?? ns stck low time t sckl 50 4 ?? ns output clock rise/fall time ? tbd ?ns delay from stck high to stfs (bl) high - slave 5 t tfsbhs 0.1 ? 46 ns delay from stck high to stfs (wl) high - slave 5 t tfswhs 0.1 ? 46 ns delay from srck high to srfs (bl) high - slave 5 t rfsbhs 0.1 ? 46 ns delay from srck high to srfs (wl) high - slave 5 t rfswhs 0.1 ? 46 ns delay from stck high to stfs (bl) low - slave 5 t tfsbls -1 ? ? ns delay from stck high to stfs (wl) low - slave 5 t tfswls -1 ? ? ns delay from srck high to srfs (bl) low - slave 5 t rfsbls -46 ? ? ns delay from srck high to srfs (wl) low - slave 5 t rfswls -46 ? ? ns stck high to stxd enable from high impedance - slave t txes ?? ns stck high to stxd valid - slave t txvs 1?25 ns stfs high to stxd enable from high impedance (first bit) - slave t ftxes 5.5 ? 25 ns stfs high to stxd valid (first bit) - slave t ftxvs 6?27 ns stck high to stxd not valid - slave t txnvs 11 ? 13 ns stck high to stxd high impedance - slave t txhis 11 ? 28.5 ns srxd setup time before srck low - slave t ss 4?? ns srxd hold time after srck low - slave t hs 4?? ns
synchronous serial interface (ssi) timing 56f826 technical data, rev. 14 freescale semiconductor 43 synchronous operation (in addition to standard external clock parameters) srxd setup time before stck low - slave t tss 4?? srxd hold time after stck low - slave t ths 4?? 1. slave mode is externally generated clocks and frame syncs 2. max clock frequency is ip_clk/4 = 40mhz / 4 = 10mhz for an 80mhz part. 3. all the timings for the ssi are given for a non-inverted seri al clock polarity (tsckp=0 in scr2 and rsckp=0 in scsr) and a non-inverted frame sync (tfsi=0 in scr2 and rfsi=0 in scsr). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverti ng the clock signal stck/srck and/or the frame sync stfs/srfs in the tables and in the figures. 4. 50% duty cycle 5. bl = bit length; wl = word length table 3-14 ssi slave mode 1 switching characteristics operating conditions: v ssio = v ss = v ssa = 0v, v dda = v ddio = 3.0?3.6v, v dd = 2.25?2.75v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz parameter symbol min typ max units
56f826 technical data, rev. 14 44 freescale semiconductor figure 3-25 slave m ode clock timing 3.11 quad timer timing table 3-15 timer timing 1, 2 operating conditions: v ssio = v ss = v ssa = 0v, v dda = v ddio = 3.0?3.6v, v dd = 2.25?2.75v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz 1. in the formulas listed, t = clock cycle. for 80mhz operation, t = 12.5ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit timer input period p in 4t+6 ? ns timer input high/low period p inhl 2t+3 ? ns timer output period p out 2t ? ns timer output high/low period p outhl 1t ? ns t ths t tss t hs t ss t rfswls t rfswhs t rfbls t rfsbhs t txhis t txnvs t ftxvs t txvs t ftxes t txes t tfswls t tfswhs t tfsbls t tfsbhs t sckl t sckw t sckh first bit last bit stck input stfs (bl) input stfs (wl) input stxd srck input srfs (bl) input srfs (wl) input srxd
serial communication interface (sci) timing 56f826 technical data, rev. 14 freescale semiconductor 45 figure 3-26 quad timer timing 3.12 serial communication interface (sci) timing figure 3-27 rxd pulse width table 3-16 sci timing 4 operating conditions: v ssio =v ss = v ssa = 0v, v dda =v ddio =3.0?3.6v, v dd = 2.25?2.75v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz characteristic symbol min max unit baud rate 1 1. f max is the frequency of operation of the system clock in mhz. br ? (f max *2.5)/(80) mbps rxd 2 pulse width 2. the rxd pin in sci0 is named rxd0 and the rxd pin in sci1 is named rxd1. rxd pw 0.965/br 1.04/br ns txd 3 pulse width 3. the txd pin in sci0 is named txd0 and the txd pin in sci1 is named txd1. 4. parameters listed are guaranteed by design. txd pw 0.965/br 1.04/br ns timer inputs timer outputs p in p inhl p inhl p out p outhl p outhl rxd sci receive data pin (input) rxd pw
56f826 technical data, rev. 14 46 freescale semiconductor figure 3-28 txd pulse width 3.13 jtag timing figure 3-29 test clock input timing diagram table 3-17 jtag timing 1, 3 operating conditions: v ssio =v ss = v ssa = 0v, v dda =v ddio =3.0?3.6v, v dd = 2.25?2.75v, t a = ?40 to +85 c, c l 50pf, f op = 80mhz 1. timing is both wait state and frequency dependent. for the values listed, t = clock cycle. for 80mhz operation, t = 12.5ns. characteristic symbol min max unit tck frequency of operation 2 2. tck frequency of operation must be less than 1/8 the processor rate. 3. parameters listed are guaranteed by design. f op dc 10 mhz tck cycle time t cy 100 ? ns tck clock pulse width t pw 50 ? ns tms, tdi data set-up time t ds 0.4 ? ns tms, tdi data hold time t dh 1.2 ? ns tck low to tdo data valid t dv ? 26.6 ns tck low to tdo tri-state t ts ? 23.5 ns trst assertion time t trst 50 ? ns de assertion time t de 4t ? ns txd sci receive data pin (input) txd pw tck (input) v m v il v m = v il + (v ih ? v il )/2 v m v ih t pw t cy t pw
jtag timing 56f826 technical data, rev. 14 freescale semiconductor 47 figure 3-30 test access po rt timing diagram figure 3-31 trst timing diagram figure 3-32 once?debug event input data valid output data valid output data valid tck (input) tdi (input) tdo (output) tdo (output ) tdo (output) tms t dv t ts t dv t ds t dh trst (input) t trst de t de
56f826 technical data, rev. 14 48 freescale semiconductor part 4 packaging 4.1 package and pin-out information 56f826 this section contains package and pin-out information for the 100-pin lqfp configuration of the 56f826. figure 4-1 top view, 56f 826 100-pin lqfp package pin 1 pin 26 pin 51 pin 76 tms tdi tdo trst v ddio v ssio a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 v ss v dd a3 a2 a1 a0 extboot orientation mark rd wr ds ps v ddio v ssio irqa irqb d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 reset d11 d12 d13 d14 d15 gpiod1 gpiod0 gpiob7 gpiob6 gpiob5 gpiob4 gpiob3 gpiob2 gpiob1 gpiob0 clko v dd v ss xtal extal v ssa v dda v ssio v ddio stck stfs std srck srfs srd tck tcs de txd0 rxd0 v ss v dd txd1 rxd1 ta0 ta1 ta2 ta3 ss miso mosi sclk gpiod7 gpiod6 v ssio v ddio gpiod5 gpiod4 gpiod3 gpiod2
package and pin-out information 56f826 56f826 technical data, rev. 14 freescale semiconductor 49 table 4-1 56f826 pin iden tification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1tms26 rd 51 srd 76 gpiod2 2tdi27 wr 52 srfs 77 gpiod3 3 tdo 28 ds 53 srck 78 gpiod4 4trst 29 ps 54 std 79 gpiod5 5v ddio 30 v ddio 55 stfs 80 v ddio 6v ssio 31 v ssio 56 stck 81 v ssio 7 a15 32 irqa 57 v ddio 82 gpiod6 8 a14 33 irqb 58 v ssio 83 gpiod7 9 a13 34 d0 59 v dda 84 sclk 10a1235d160 v ssa 85 mosi 11 a11 36 d2 61 extal 86 miso 12a1037d362xtal87ss 13 a9 38 d4 63 v ss 88 ta3 14 a8 39 d5 64 v dd 89 ta2 15 a7 40 d6 65 clko 90 ta1 16 a6 41 d7 66 gpiob0 91 ta0 17 a5 42 d8 67 gpiob1 92 rxd1 18 a4 43 d9 68 gpiob2 93 txd1 19 v ss 44 d10 69gpiob394v dd 20 v dd 45 reset 70 gpiob4 95 v ss 21 a3 46 d11 71 gpiob5 96 rxd0 22 a2 47 d12 72 gpiob6 97 txd0 23 a1 48 d13 73 gpiob7 98 de 24 a0 49 d14 74 gpiod0 99 tcs 25 extboot 50 d15 75 gpiod1 100 tck
56f826 technical data, rev. 14 50 freescale semiconductor figure 4-2 100-pin lqpf m echanical information please see www.freescale.com for the most current case outline. notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -ab- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -t-, -u-, and -z- to be determined at datum plane -ab-. 5. dimensions s and v to be determined at seating plane -ac-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -ab-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.350 (0.014). dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.070 (0.003). 8. minimum solder plate thickness shall be 0.0076 (0.003). 9. exact shape of each corner may vary from depiction. ae ae ad seating (24x per side) r gauge plane detail ad section ae-ae s v b a 96x x e c k h w d f j n 9 dim min max min max inches millimeters a 13.950 14.050 0.549 0.553 b 13.950 14.050 0.549 0.553 c 1.400 1.600 0.055 0.063 d 0.170 0.270 0.007 0.011 e 1.350 1.450 0.053 0.057 f 0.170 0.230 0.007 0.009 g 0.500 bsc 0.020 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 q 1 5 1 5 r 0.150 0.250 0.006 0.010 s 15.950 16.050 0.628 0.632 v 15.950 16.050 0.628 0.632 w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref case 842f-01 -t- s t-u s 0.15(0.006) z s ac s t-u s 0.15(0.006) z s ac s t-u s 0.15(0.006) z s ac -u- s t-u s 0.15(0.006) z s ab -z- -ac- g plane -ab- s t-u m 0.20(0.008) z s ac 0.100(0.004) ac q m 0.25 (0.010)
thermal design considerations 56f826 technical data, rev. 14 freescale semiconductor 51 part 5 design considerations 5.1 thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: where: t a = ambient temperature c r ja = package junction-to-ambie nt thermal resistance c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a j unction-to-case thermal resistance and a case-to-ambient thermal resistance: equation 2: where: r ja = package junction-to-ambie nt thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w r jc is device-related and ca nnot be influenced by the user. the user controls the thermal environment to change the case-to-ambien t thermal resistance, r ca . for example, the user ca n change the air flow around the device, add a heat sink, change the mounting ar rangement on the printed circuit board (pcb), or otherwise change the thermal diss ipation capability of the area su rrounding the device on the pcb. this model is most useful for ceramic pa ckages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for cera mic packages, in situations where the heat flow is split between a path to the case a nd an alternate path through the pcb, analysis of the device thermal performance may need the additional modeling capabili ty of a system-level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperat ure of the pcb to which the package is mounted. again, if the estimations obtained from r ja do not satisfactorily answer whether the thermal performance is adequate, a sy stem-level model may be appropriate. definitions: a complicating factor is the existe nce of three common definitions fo r determining the junction-to-case thermal resistance in plastic packages: ? measure the thermal resistance from the junction to th e outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. this is done to minimize temperature variation across the surface. ? measure the thermal resistance from the junction to where the leads are attached to the case. this definition is approximately equal to a junc tion-to-board thermal resistance. t j t a p d r ja () + = r ja r jc r ca + =
56f826 technical data, rev. 14 52 freescale semiconductor ? use the value obtained by the equation (t j ? t t )/p d , where t t is the temperature of the package case determined by a thermocouple. the thermal characterization parameter is measured per jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top ce nter of the package case. the th ermocouple should be positioned so that the thermocouple junction re sts on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. when heat sink is used, the junction temperature is determined from a ther mocouple inserted at the interface between the case of the p ackage and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearan ce is important to mi nimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with th is technique, many engine ers measure the heat si nk temperature and then back-calculate the case temperatur e using a separate measurement of the thermal resistance of the interface. from this case temperat ure, the junction temperature is de termined from th e junction-to-case thermal resistance. 5.2 electrical design considerations use the following list of considerat ions to assure correct operation: ? provide a low-impedance path from the board power supply to each v dd, v ddio, and v dda pin on the controller, and from the board ground to each v ss, v ssio, and v ssa (gnd) pin. ? the minimum bypass requ irement is to place 0.1 f capacitors positioned as clos e as possible to the package supply pins. the recommended bypass configuration is to place one bypass capacitor on each of the v dd /v ss pairs, including v dda /v ssa and v ddio /v ssio. ceramic and tantalum capacitors tend to provide better performance tolerances. ? ensure that capacitor leads and associated printe d circuit traces that connect to the chip v dd, v ddio, and v dda and v ss, v ssio, and v ssa (gnd) pins are less than 0.5 inch per capacitor lead. ? bypass the v dd and v ss layers of the pcb with approximately 100 f, preferably with a high-grade capacitor such as a tantalum capacitor. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
electrical design considerations 56f826 technical data, rev. 14 freescale semiconductor 53 ? because the controller?s output signals have fast rise and fall times, pcb trace le ngths should be minimal. ? consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in system s with higher capacitive loads that co uld create higher transient currents in the v dd and v ss circuits. ? take special care to minimize noise levels on the vref, v dda and v ssa pins. ? when using wired-or mode on the spi or the irqx pins, the user must provide an external pull-up device. ? designs that utilize the trst pin for jtag port or once module functionality (such as development or debugging systems) should allow a means to assert trst whenever reset is asserted, as well as a means to assert trst independently of reset . trst must be asserted at power up for proper operation. designs that do not requir e debugging functionality, such as consumer products, trst should be tied low. ? because the flash memory is programmed through the jtag/once port, designers should provide an interface to this port to allo w in-circuit flash programming.
56f826 technical data, rev. 14 54 freescale semiconductor part 6 ordering information table 6-1 lists the pertinent information needed to pl ace an order. consult a freescale semiconductor sales office or authorized di stributor to determine availability and to order parts. *this package is rohs compliant. table 6-1 56f826 ordering information part supply voltage package type pin count ambient frequency (mhz) order number 56f826 3.0?3.6 v 2.25-2.75 v plastic quad flat pack (lqfp) 100 80 dsp56f826bu80 56f826 3.0?3.6 v 2.25-2.75 v plastic quad flat pack (lqfp) 100 80 dsp56f826bu80e *
electrical design considerations 56f826 technical data, rev. 14 freescale semiconductor 55
how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc. 2005. all rights reserved. dsp56f826 rev. 14 01/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical ex perts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp .

▲Up To Search▲

Price & Availability of DSP56F826E

	To Download DSP56F826E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .